Intel P80C31

Definition

The Intel P80C31 is an 8-BIT MICROCONTROLLER in the MCS-51 family ( 8051-class core) in a ROMLESS version, meaning it has no on-chip program ROM. It is intended for embedded systems where firmware resides in external memory (typically EPROM or FLASH) while keeping the typical family integration: CPU, internal RAM, I/O ports, timers, and a serial interface on the same chip.

Key feature: ROMLESS and external memory up to 64K

The defining point of the P80C31 is that:

• Program memory is external and addressable up to 64K (code space).

• An external data space up to 64K is also available ( XDATA space, typically external RAM or memory-mapped peripherals).

This approach was very useful when firmware had to be larger than the typical on-chip ROM of other family members, or when maximum flexibility was needed during development and maintenance (updating external memory without replacing the microcontroller).

8-bit internal architecture (what is inside)

The P80C31 keeps the classic MCS-51 functional profile:

• 8-BIT CPU with the register model and instruction set of the 8051 family.

• Internal RAM 128 × 8 bytes for variables, stack, and small buffers.

• 32 programmable I/O lines (parallel ports).

• 2 × 16-BIT TIMER/COUNTER blocks for time-base, counting, and timing.

• One programmable serial port (typically a full-duplex UART) for communication and diagnostics.

• An interrupt system with multiple sources, useful for event handling (timers, serial, external inputs).

• On-chip oscillator/clock interface for crystal or external clock source.

Technology and power (CMOS / CHMOS, saving modes)

Intel 80C31 variants are associated with CMOS/CHMOS processes, with typical practical benefits:

• Generally lower power consumption than comparable non-CMOS implementations.

• “Static” operation capability (in many variants: wide operating frequency range, down to very low frequencies).

• Software power-reduction modes: IDLE and POWER DOWN (in IDLE the CPU stops while some peripherals can keep running; in POWER DOWN the oscillator also stops while preserving RAM).

Board-level integration (what is needed around the chip)

In a typical P80C31 design you need:

• Power supply and decoupling.

• Clock (crystal on oscillator pins) and RESET.

• External program memory (EPROM/FLASH) connected to the address/data bus and code-read control signals.

• Optional external RAM/peripherals in the data space ( XDATA ) if internal RAM is insufficient.

• Connections from I/O ports to sensors, latches, drivers, relays, LEDs, or an expansion bus.

Sketch of the most important connections

                 ┌──────────────────────────────┐
                 │          EPROM / FLASH        │
                 │      (program up to 64K)      │
                 └──────────────┬───────────────┘
                                │ code bus (addr/data + control)
                                ▼
                       ┌──────────────────┐
                       │   INTEL P80C31   │
                       │ ROMLESS 8-BIT MCU│
                       │ 128 B RAM        │
                       │ 32 I/O + UART    │
                       │ 2 × 16-BIT TIMER │
                       └───────┬──────────┘
                               │
                               ├────────► Parallel I/O → sensors / drivers / latches / LEDs
                               │
                               ├────────► UART → serial (debug / peripherals)
                               │
                               ├────────► TIMERS → time-base / counting / interrupts
                               │
                               └────────► (opt.) XDATA → external RAM / peripherals up to 64K

Table 1 – Identification data and specifications (English)

Table 2 – Operational and design aspects (English)