Zilog Z0842884PSC is a PIO (parallel input/output),an interface IC that adds two programmable parallel ports to a Z80-based system, reducing CPU overhead for parallel I/O, handshaking, and interrupt-driven transfers. An IC in the Z0842884PSC class belongs to the Zilog Z80 PIO family and provides two independent 8-bit ports, port A and port B, intended for peripherals such as keyboards, printers, TTL logic, and industrial control devices.

For the specific code Z0842884PSC, it is commonly listed as a Z80 PIO in a 40-pin DIP package with an indicative 4 MHz speed grade (exact NMOS/CMOS revision and speed grading can vary by production and suffix conventions, so verifying the exact marking and the corresponding datasheet is recommended).

What it adds beyond simple latches

A PIO is not just “two output registers”. It integrates features that matter in embedded and vintage Z80 systems:

• Hardware handshaking using ready and strobe lines to synchronize transfers with slower/asynchronous devices.

• Programmable interrupts, so the CPU can avoid continuous polling.

• Interrupt daisy chaining via IEI/IEO to build a deterministic priority chain among Zilog peripherals without heavy external glue logic.

• Multiple operating modes to adapt the same chip to byte transfers or fine-grained bit control.

Core operating modes (Z80 PIO family)

The classic four modes are:

• Mode 0 (output): 8-bit output port with handshake semantics.

• Mode 1 (input): 8-bit input port with handshake semantics.

• Mode 2 (bidirectional): typically available on port A, using additional handshake/interrupt resources to coordinate bidirectional transfers.

• Mode 3 (bit control): each bit can be independently configured as input or output, with interrupts generated on programmable logical conditions and programmable active level.

Handshaking and interrupts

In byte-oriented modes, each port uses two handshake signals:

• RDY (ready): indicates readiness or data availability (depending on mode).

• STB (strobe): asserted by the peripheral to time/confirm a transfer.

With interrupts enabled, the PIO can request service when transfers occur or when a programmed status condition is met. For full efficiency, Z80 systems commonly use interrupt mode 2, where the device supplies an interrupt vector used to index an interrupt service routine pointer.

CPU interface (Z80 bus view)

At the bus level, a PIO typically connects to:

• DATA0–DATA7

• Z80 I/O control signals such as /IORQ, /RD, /WR, and often /M1 for interrupt-related protocol

• a chip-select (/CE) from address decode logic

• internal select lines (often seen as A0/A1 equivalents) to select port A vs port B and data vs control access

This enables a conventional mapping where the CPU separately accesses each port’s data and control registers.

Table 2 – Identification data and specifications