UltraSparc II – second-generation UltraSparc, SPARC V9 CPU for servers and workstations

Definition

UltraSparc II is the second generation of the UltraSparc family developed by Sun Microsystems, and it implements the 64-bit SPARC V9 architecture. It was introduced to the market starting in 1997, with the first versions around 250 MHZ, and it was used primarily in server and workstation systems.

A key point is binary compatibility: SPARC V9 preserves application continuity with earlier SPARC generations, allowing existing software to run (with the usual constraints related to operating system/ABI and the 32/64-bit transition).

Frequency evolution: from 250 MHZ to the last revisions

The first commercial series starts at 250 MHZ. With process and revision evolution, frequencies increase significantly.

It is important to distinguish between “UltraSparc II” and the real-world scope in which it is often discussed: in documentation and in the market you can find CPUs/modules and platforms with different final values (for example 450 MHZ modules, systems supporting up to 480 MHZ, and in some technical summaries even higher peaks attributed to revisions/variants of the line). In practice, 450 MHZ is a very common value because it is associated with upgrade modules and widely deployed configurations, but it is not the only “high” value that appears in family specifications.

SPARC V9 architecture and binary compatibility

UltraSparc II is a full implementation of SPARC V9. From a design perspective this means:

A clear separation between ISA and microarchitecture: software “sees” SPARC V9, while hardware delivers performance through pipeline design, branch prediction, advanced dependency handling, and memory-subsystem optimizations.

Binary compatibility across the SPARC family: V9 was designed to preserve continuity of software developed for previous SPARC implementations, with strong support for “enterprise” environments (toolchains, operating systems, and server applications).

Memory subsystem and cache: external E-cache and configuration flexibility

A typical UltraSparc II system feature is an L2 cache external to the core, often referred to as E-cache (external cache), with sizes and speeds that vary depending on the platform/CPU module.

In practical terms this affects:

Real performance: external cache size and speed have a major impact on server workloads (databases, file services, networking).

Board/module design: the CPU requires a coherent implementation of the path to the cache and to the system controller, with layout and timing constraints.

Scalability and multiprocessing: a server orientation

UltraSparc II was designed for scalable systems: both the microarchitecture and the system interface are aimed at multiprocessing configurations. Practically:

In “glueless” configurations it typically scales to up to 4-way systems without complex external coherence logic.

With appropriate platform architectures and system controllers, the line was also used in systems with a higher CPU count, typical of servers of that era.

Sketch of the most important connections

                 system bus + control (platform interconnect)
        ┌──────────────────────────────────────────────────────────┐
        │               system controller / chipset                 │
        │   arbitration, memory, I/O bridge, coherence (platform)   │
        └───────────────────────────────┬──────────────────────────┘
                                        │
                                        ▼
                           ┌─────────────────────────────┐
                           │         UltraSparc II        │
                           │      SPARC V9 64-bit core    │
                           │   interface toward E-cache   │
                           └─────────────┬───────────────┘
                                         │
                                         ├────────► E-cache (external L2, variable sizes)
                                         └────────► RAM + I/O (via system controller)

Table 1 – Identification data and specifications

Table 2 – Operational and design considerations