AMD AM7990: LANCE (Local Area Network Controller for Ethernet)

The AMD AM7990DC/60 was a LANCE Network Controller, used in the MicroVAX 3100, DEC M-7516 DELQA systems, in DEC servers, in the VS2000, Symmetric 375 which used the NSC 32016 processor

The project dates back to 1983 and was copyrighted in 1994.

Definition

AMD AM7990, is a 10 Mb/s Ethernet MAC controller designed to connect a host system (CPU + RAM) to an IEEE 802.3/Ethernet LAN by offloading the repetitive and time-critical parts of Layer 2: CSMA/CD medium access, frame handling, CRC generation/checking, collision and retry management, address filtering, and high-throughput data movement via DMA using descriptor rings stored in host memory.

It is important to separate responsibilities: Am7990 is a MAC/controller. In typical classic designs it relies on external components for the physical interface (Manchester/AUI signaling and line interface), often through a companion chain such as an SIA/ENDEC plus transceiver.

Why it is used

On a vintage Ethernet interface, without a dedicated controller the CPU would need to copy data, build frames, handle collision timing, and keep up with strict medium access rules. With LANCE the model becomes:

• The CPU builds structures (buffers and descriptors) in RAM.

• Am7990 performs bus-master DMA, updates completion/status in RAM, and raises interrupts.

• The CPU focuses on orchestration: initialization, keeping RX buffers posted, queueing TX frames, and handling events.

Logical architecture: three key objects in memory

Operation revolves around three primary RAM objects:

1. Initialization block: configuration (MAC address, mode bits, ring pointers, and related parameters).

2. Receive descriptor ring: RX descriptors pointing to buffers ready to be filled.

3. Transmit descriptor ring: TX descriptors pointing to buffers to be transmitted.

A fundamental mechanism is descriptor ownership, often represented by an OWN bit. It indicates whether a descriptor/buffer is currently owned by the controller (the controller may read/write it) or by the host (the host may recycle or modify it).

Receive flow (RX)

• The driver allocates N receive buffers and prepares N RX descriptors in the RX ring, typically setting OWN=1 (controller owns).

• When a valid frame arrives, LANCE DMA-writes the frame into the target buffer(s), updates length and status flags (CRC error, framing, overflow, etc.), then returns ownership (typically OWN=0) and optionally interrupts.

• The driver scans completed RX descriptors, passes packets upward, restores or replaces buffers, and sets OWN=1 again to repost them to the controller.

Transmit flow (TX)

• The driver prepares a TX descriptor pointing to the frame buffer (or a chained buffer set), sets start/end markers (commonly STP/ENP), and hands ownership to the controller (OWN=1).

• LANCE DMA-reads the payload, transmits under CSMA/CD rules, updates completion status (success, collisions, retries, underrun, etc.), then returns OWN=0 and signals completion.

Filtering, status, and diagnostics

Typical LANCE-class capabilities include:

• Address filtering for unicast (its own MAC), broadcast, and selected multicast modes depending on configuration.

• Per-frame status and error reporting via descriptor flags and controller status registers.

• Diagnostic support in the documented feature set, including TDR (time-domain reflectometer) in certain configurations, historically useful for locating discontinuities on coax-based Ethernet segments.

Sketch of the most important connections

                 ┌──────────────────────────────┐
                 │           CPU / host          │
                 │  driver + buffer management   │
                 └──────────────┬───────────────┘
                                │ host bus (I/O or memory-mapped)
                                │ + IRQ + reset
                                ▼
                        ┌─────────────────┐
                        │ AMD Am7990      │
                        │ LANCE (MAC)     │
                        │ DMA + ring desc │
                        └──────┬──────────┘
                               │ DMA to RAM
                               ▼
                 ┌──────────────────────────────┐
                 │ Shared RAM                    │
                 │ - initialization block        │
                 │ - RX descriptor ring + buffers│
                 │ - TX descriptor ring + buffers│
                 └──────────────────────────────┘
                               │
                               ▼
            ┌───────────────────────────────┐
            │ SIA / ENDEC + transceiver     │
            │ (Manchester encoding + line)  │
            └──────────────┬────────────────┘
                           ▼
                       Ethernet (AUI / 10 Mb)

Table 1 – Identification and main characteristics

Table 2 – Memory structures and typical fields