Intel A82596SX-20

Ethernet CSMA/CD LAN controller with 16/32-bit bus mastering, 82586 compatibility, and an i386-optimized interface

The Intel A82596SX-20 is an Ethernet CSMA/CD network controller designed to perform MAC (medium access control) functions autonomously, reducing the load on the host CPU. Although it is sometimes loosely associated with early “Pentium-era” systems (and informally referred to as “Pentium 1” in some historical platform contexts), it is not a CPU: it is a high-performance networking component that integrates framing, buffer handling, DMA/bus mastering, and diagnostics within the I/O subsystem.

The SX-20 variant targets an interface optimized for 16-bit platforms (while supporting 16/32-bit bus mastering), operating at a 20 MHZ clock with a stated bus bandwidth up to 66 MB/s.

CSMA/CD MAC functions and IEEE 802.3 compliance

Performs complete CSMA/CD MAC functions independently of CPU
The chip performs MAC functions independently, handling media access, transmit/receive, and frame-level flow control. The practical effect is fewer interrupts and less per-packet CPU work.

IEEE 802.3 frame delimiting
It integrates IEEE 802.3 frame delimiting, improving interoperability and robustness in packet handling.

Industry-standard LAN support (10BASE) and proprietary networks

Supports industry standard LANs
It supports multiple 10BASE standards, including 10BASE-T, 10BASE5, 10BASE2, 1BASE5 (StarLAN), and the proposed 10BASE-F. In practice, this covers very different physical topologies and cabling types (twisted pair, coax, and fiber in period deployments).

Proprietary CSMA/CD networks up to 20 Mb/s
It also supports proprietary CSMA/CD networks up to 20 Mb/s, useful in industrial contexts or specialized installations beyond classic Ethernet.

On-chip memory management and buffer structures

On-chip memory management
The controller includes logic for managing buffers and queues, with key features:

• Automatic buffer chaining, to link buffers without continuous CPU intervention.

• Buffer reclamation after receiving bad frames, with an option to save bad frames when required (useful for diagnostics).

• Support for 32-bit memory addressing formats, both segmented and linear (flat), easing integration with different networking software memory models.

82586 software compatible
Software compatibility with the 82586 reduces porting cost: drivers and data structures can often be reused or adapted with fewer changes.

Optimized CPU interface and endianness support

Optimized CPU interface
Interfaces are optimized for i386-class platforms:

• 82596DX interface optimized for 32-bit i386 systems.

• 82596SX interface optimized for 16-bit i386 systems.

Big endian and little endian
It supports both big endian and little endian byte ordering, which is practically useful when integrating with systems or buses where byte order may vary, or when sharing data structures across heterogeneous components.

16/32-bit bus mastering and transfer performance

High-performance 16/32 bit bus master interface
The controller can operate as a bus master, moving data directly between the network and system memory without CPU-managed intermediate copies. Provided characteristics include:

• Bus bandwidth up to 66 MB/s.

• 20 MHZ clock, two clocks per transfer.

• Bus throttle timers, to tune bus-master aggressiveness and reduce impact on other devices.

• Transfers at 100% of serial bandwidth (goal: avoid losing network throughput due to bus limits).

• FIFOs: 128-byte receive and 64-byte transmit, helping absorb bursts and reduce jitter when memory latency varies.

Network management and diagnostics

Network management and diagnostics
It includes serviceability features:

• Monitor mode, for traffic observation.

• 32-bit statistical counters, for measurement and troubleshooting.

• Self-test diagnostics, for integrity checks and quick fault isolation.

• Configurable initialization root for data structures, simplifying driver startup and configuration.

Technology and electrical requirements

High-speed, 5-V, CHMOS IV technology
It is built in CHMOS IV technology at 5 V, aligning with PC and industrial platforms of the era, with emphasis on high speed and robust integration.

Sketch of the most important connections

        Ethernet network (10BASE-T/5/2, etc.)
                    │
                    ▼
         ┌─────────────────────────┐
         │  Intel A82596SX-20       │
         │  CSMA/CD MAC + FIFO      │
         │  16/32-bit bus master    │
         └───────────┬─────────────┘
                     │ system bus / DMA
                     ▼
        ┌───────────────────────────────┐
        │ chipset + RAM                  │
        │ buffer / descriptor structures │
        └───────────┬───────────────────┘
                    │
                    ▼
          system CPU (i386/compatible)

Table 1 – Identification data and specifications

Table 2 – Operational and design considerations