FPGA (FIELD PROGRAMMABLE GATE ARRAY)

Definition

An FPGA (FIELD PROGRAMMABLE GATE ARRAY) is a reconfigurable digital integrated circuit that lets you implement custom hardware logic after manufacturing: combinational networks, state machines, pipelines, interfaces, accelerators, and even entire CPU “soft-cores”. Unlike a CPU or MCU, which execute instructions sequentially on a fixed architecture, an FPGA lets you “write hardware” by directly defining connections and timing at the level of logic blocks and internal routing.

“Field programmable” means it can be programmed “in the field”, by the user or system integrator, through a configuration file (bitstream) loaded at boot or stored in an external/on-chip non-volatile memory (family-dependent).

Key concept: reconfigurable hardware

On an FPGA you do not program an instruction stream as on a CPU: you describe a hardware structure that operates in parallel. As a result:

• Many operations happen simultaneously (hardware parallelism).

• Latency can be very low and controllable (pipelines and timing).

• Performance depends on design quality (architecture, floorplanning, timing constraints), not only on clock frequency.

Typical internal structure

An FPGA consists of multiple classes of resources interconnected together:

• Configurable logic blocks (CLB/LE): base units containing LUT (lookup tables) for combinational logic, flip-flops for sequential logic, and local multiplexers.

• Interconnect / routing network: a matrix of programmable connections linking logic blocks and internal peripherals; it is crucial for performance and power.

• Block RAM (BRAM): dedicated on-chip memories usable as dual-port RAM, FIFO, buffers, ROM for coefficients, and more.

• DSP slices: optimized arithmetic blocks (multipliers, MAC, adders) for filters, FFT, classic AI workloads, motor control.

• PLL/MMCM and clock network: clock generation, multiply/divide, low-skew distribution.

• Programmable I/O: I/O banks with selectable standards (LVTTL, LVCMOS, LVDS, etc.), often with SERDES for high-speed signals.

• Hard IP (device-dependent): fixed-function blocks such as multi-gigabit transceivers, DDR controllers, PCIe, Ethernet MAC, and sometimes integrated CPU cores (SoC FPGA).

Development flow (toolchain)

Designing for an FPGA means transforming a logical description into a physical configuration:

1. Hardware description in HDL (VHDL/Verilog/SystemVerilog) or via HLS (C/C++→RTL) where applicable.

2. Synthesis: converts the logic into a netlist of primitives (LUT, FF, BRAM, DSP).

3. Place & route: places resources on the device and routes the interconnect.

4. Timing closure: verification and refinement to meet timing constraints (setup/hold, target clock).

5. Bitstream generation and programming/configuration of the device.

The critical step, especially for complex designs, is TIMING CLOSURE: ensuring all paths meet the required clock, including multi-clock paths and constraints such as false paths/multicycle.

Clocking and timing (why it differs from software)

In an FPGA it is normal to have multiple clock domains and deep pipelines. Practical concepts:

• FMAX: maximum achievable clock frequency after place & route.

• Latency: number of cycles from input to output (often deterministic).

• Throughput: how many operations per cycle can be sustained (often 1/cycle in a pipeline).

• CDC (CLOCK DOMAIN CROSSING): crossings between different clocks that require synchronizers, asynchronous FIFOs, or handshake logic.

Configuration and persistence

Many FPGA families rely on internal SRAM configuration: at power-on they must load the bitstream from an external memory (SPI FLASH, QSPI, etc.) or from a host. Other families integrate non-volatile configuration storage. This impacts:

• Boot/configuration time.

• Bitstream protection (encryption/authentication where supported).

• Field update strategies (dual image, fallback).

Typical advantages

• Flexibility: hardware can be updated and optimized over time.

• Parallelism: accelerates streaming and pipelined workloads (DSP, video, networking).

• Low latency: useful for real-time control and deterministic protocols.

• Integration: multiple interfaces and accelerators can coexist on one device.

• Prototyping: validates hardware architectures before an ASIC.

Typical limitations

• Unit cost often higher than MCU/MPU for the same function at low/medium volumes.

• Power: routing and reconfigurable fabric can consume more than an equivalent ASIC.

• Design complexity: requires digital architecture skills, timing, CDC, and hardware debug.

• Boot/configuration: SRAM-based devices need a bitstream loading infrastructure.

Sketch of the most important connections

                 ┌──────────────────────────────┐
                 │            HOST CPU/MCU       │
                 │ configuration + control       │
                 └──────────────┬───────────────┘
                                │ (SPI/QSPI/JTAG or bus)
                                ▼
                       ┌──────────────────┐
                       │       FPGA       │
                       │  LUT/FF + BRAM   │
                       │  DSP + routing   │
                       │  PLL + I/O banks │
                       └───┬───────────┬──┘
                           │           │
                     Digital I/O   High-speed links*
                    (GPIO, LVDS)   (SERDES, PCIe, ETH)
                           │           │
                           ▼           ▼
                 Sensors/actuators   Network / DDR / peripherals
* Device/model dependent.

Table 1 – Typical FPGA resources 

Table 2 – Summary comparison: FPGA vs CPU/MCU