VIA C3 800 MHZ – low-power x86 CPU (Ezra core) with a 133 MHZ bus and 64K L1/L2 caches, tested on Shuttle SV24
The VIA C3 800 MHZ is a low-power x86 CPU produced by VIA Technologies, based on the production codename Ezra. It is intended for compact and quiet systems (small form factor desktops and barebones), where low power draw, platform simplicity, and x86 OS/application compatibility matter.
The provided technical profile indicates a 0.13 micron process, a 52 mm² die area, a 133 MHZ bus, 1.35 V core voltage, a 12-stage ALU pipeline, and a cache hierarchy of 64K L1 + 64K L2. A clock-management range of 500 MHZ to 1.4 GHZ is also indicated, consistent with dynamic scaling mechanisms used to balance performance and power.
Production codename: Ezra and “low power” positioning
The Ezra codename identifies a C3 generation focused on efficiency and integration on cost-effective platforms. Practically, the goal is not maximum peak throughput, but adequate performance with reduced power and broad compatibility with common chipsets and memory configurations.
Process, die size, and voltage: 0.13 micron, 52 mm², 1.35 V
0.13 micron and 52 mm² describe a relatively compact die. In practice, a small die and 1.35 V core voltage are consistent with:
easier thermal management in small chassis
lower cooling requirements (often simpler heatsink/fan solutions)
platforms optimized for low noise and reduced power consumption
Bus: 133 MHZ and platform impact
The 133 MHZ bus is important because it influences available bandwidth to the chipset and memory. Operationally:
it improves the CPU’s ability to be fed versus lower-bus platforms
real performance depends on chipset, RAM type/latency, and motherboard routing quality
Pipeline: 12-stage ALU pipeline
A 12-stage ALU pipeline indicates significant depth for a CPU in this class. In practice:
it helps reach higher clock frequencies for a given process
it increases sensitivity to branches and mispredictions (more potential bubbles), so workload type matters (branch-heavy vs streaming)
Cache: 64K L1 and 64K L2
The stated 64K L1 and 64K L2 caches define a relatively small hierarchy, consistent with low-cost/low-power targets. In practice:
on small working sets, the CPU can remain “in cache” more often
on large datasets (heavy compression, builds, intense multitasking), dependence on memory bandwidth and chipset behavior increases
Clock management: 500 MHZ to 1.4 GHZ
The 500 MHZ → 1.4 GHZ range suggests dynamic clock scaling (lower in idle, higher under load). Practical implications:
power and temperature can drop significantly at idle
under load, frequency rises to keep responsiveness, but performance remains constrained by cache and platform memory bandwidth
Comparative test: Shuttle SV24 with VIA C3 800 MHZ vs Intel Celeron 900 MHZ
The cited test compares a Shuttle SV24 barebone system in two CPU configurations: VIA C3 800 MHZ and Intel Celeron 900 MHZ. The platform configuration (from the image) is described as:
Motherboard: Shuttle FV24
Chipset: VIA PL133
North bridge: VT8604
South bridge: VT82C686B
Memory: 256 MB (1 DIMM)
Memory type: PC100 SDRAM CAS 2
Graphics: S3 Integrated S3 Savage4
Storage: IBM 75GXP 40 GB 7200 RPM ATA/100
Operating system: Windows XP Professional
Practically, this comparison highlights architectural and platform differences: the C3 targets efficiency and a 133 MHZ bus, while the 900 MHZ Celeron is a more performance-oriented reference in the same era. PC100 memory and integrated graphics also make the test sensitive to RAM bandwidth and driver quality, not only CPU characteristics.
Sketch of the most important connections
133 MHZ system bus + chipset (memory/I-O)
┌──────────────────────────────────────────────────────────┐
│ Shuttle FV24 motherboard + VIA PL133 │
│ north VT8604, south VT82C686B │
│ PC100 SDRAM, integrated graphics, ATA/100, I/O │
└───────────────────────────────┬──────────────────────────┘
│
▼
┌─────────────────────────────┐
│ VIA C3 800 MHZ │
│ Ezra core │
│ 133 MHZ bus, 1.35 V │
│ L1 64K, L2 64K │
│ 12-stage ALU pipeline │
└─────────────┬───────────────┘
│
├────────► RAM (via chipset)
└────────► I/O (graphics/ATA/network via southbridge)
Table 1 – Identification data and specifications
| Characteristic | Indicative value |
|---|
| Device | VIA C3 800 MHZ |
| Production codename | Ezra |
| Process | 0.13 micron |
| Die size | 52 mm² |
| Bus | 133 MHZ |
| Core voltage | 1.35 V |
| Pipeline | 12-stage ALU |
| L1 cache | 64K |
| L2 cache | 64K |
| Stated clock (scaling) | 500 MHZ – 1.4 GHZ |
Table 2 – Test platform and comparison (Shuttle SV24)
| Aspect | Practical meaning |
|---|
| CPUs compared | VIA C3 800 MHZ vs Intel Celeron 900 MHZ |
| Front-side bus | 133 MHZ (C3) vs 100 MHZ (Celeron) |
| Motherboard | Shuttle FV24: compact barebone platform |
| Chipset / bridges | VIA PL133 + VT8604 + VT82C686B: defines RAM and I/O bandwidth |
| Memory | 256 MB PC100 SDRAM CAS 2: potential bottleneck on memory-bound workloads |
| Graphics | Integrated S3 Savage4: impacts 2D/3D workloads and drivers |
| Storage | IBM 75GXP 40 GB ATA/100: affects load times and disk I/O |
| Operating system | Windows XP Professional: typical desktop/office scenario of the era |
