DEC DC303-002F / DC303-203F – two-die F-11 chipset (302 + 303) for PDP-11-class architecture

Definition

The DEC DC303-002F and DEC DC303-203F are the two chips that together form the DEC F-11: a CPU implemented as a two-IC chipset identified as 302 and 303. The F-11 implements PDP-11-class compatibility (a 16-bit architecture), but in a more integrated form compared to board-level CPUs built from discrete logic.

The provided operating data for this implementation are: 3.6 MHZ clock, 22-bit bus, 6.0 µm process, and approximately 29,000 transistors in total.

Two-chip architecture: why 302 + 303

The fact that the F-11 is split into two chips (302 and 303) is typical of transitional “chipset CPU” designs: core execution-state functions (status, registers, ALU) are separated from more microcoded/control-oriented functions (ROM/PLA and sequencing logic).

In practice:

The 302 is the block closest to the “CPU core” (state, ALU, architectural registers).

The 303 provides control resources such as ROM and PLA, used for decoding and sequencing internal operations, along with other support functions.

Technology parameters and system interface

Clock (3.6 MHZ)
At 3.6 MHZ, the performance profile is consistent with PDP-11-compatible LSI minicomputer-class systems, where control-path efficiency and cycles per instruction strongly influence real throughput.

Bus (22-bit)
A 22-bit bus implies addressing capability up to 2²² bytes (4 MB) of physical space, which is important because it goes beyond the “base” limits of many 16-bit CPUs with shorter buses and enables systems with larger memory and I/O maps typical of minicomputer platforms.

Transistor count and process node
Approximately 29,000 transistors and a 6.0 µm process place the design in an era where density was sufficient to integrate essential control and datapath logic, but not enough to make the whole CPU “monolithic”; hence the two-chip partition.

Chip 302: PSW, 16-bit arithmetic, PDP-11 registers, and related functions

The 302 chip incorporates functions directly tied to the architectural behavior of the CPU, including:

PSW (processor status word)
The PSW is the processor status word: it contains condition flags (e.g., zero, negative, carry, overflow), control bits, and information used for exception/interrupt handling and execution flow. Practically, it is the “compatible state” that low-level software expects to read and manipulate.

16-bit arithmetic functions
16-bit arithmetic is consistent with the PDP-11 ISA (the 16-bit word is the central data format). In practice, this is where the ALU logic lives, including flag updates in the PSW based on results.

PDP-11 architectural register set
The PDP-11 CPU is known for its general-purpose registers with conventional roles (including stack pointer and program counter). The 302 includes the part that implements and manages these registers (or their fundamental logic), ensuring operational compatibility.

Other functions
Beyond the core blocks, the 302 includes additional support logic needed to complete the datapath (for example internal transfer paths, local control logic, and auxiliary execution functions).

Chip 303: ROM and PLA (microcontrol) and related functions

The 303 chip includes resources typical of the CPU “control” side:

ROM 414
The presence of a ROM (identified as 414) suggests control contents (microsequences, tables, or decode data) that drive instruction execution and/or handle non-trivial internal sequences.

PLA 138 × 23-bit
A PLA (programmable logic array) of 138 × 23 bits is a classic resource for combinational decoding and internal control-signal generation. Practically: the PLA takes opcode/condition inputs and produces vectors of control signals that orchestrate the datapath and bus cycles.

Other functions
In addition to ROM and PLA, the 303 integrates further control/support logic (sequencing, decoding, state handling), completing what is not “pure datapath” in the 302.

Sketch of the most important connections

                 system bus (address/data/control) 22-bit
        ┌──────────────────────────────────────────────────────────┐
        │                 platform (memory + I/O)                   │
        │   RAM/ROM, peripherals, interrupts, arbitration, timing   │
        └───────────────────────────────┬──────────────────────────┘
                                        │
                                        ▼
                           ┌─────────────────────────────┐
                           │        DEC F-11 chipset      │
                           │     composed of two chips:   │
                           │     302 + 303                │
                           │     3.6 MHZ clock            │
                           └─────────────┬───────────────┘
                                         │
                     ┌───────────────────┴───────────────────┐
                     ▼                                       ▼
          ┌──────────────────────┐                ┌──────────────────────┐
          │ Chip 302 (datapath)  │                │ Chip 303 (control)   │
          │ PSW, 16-bit ALU,     │                │ ROM 414, PLA 138×23  │
          │ PDP-11 registers     │                │ and control logic     │
          └──────────────────────┘                └──────────────────────┘

Table 1 – Identification data and specifications

Table 2 – Functional split: 302 vs 303