The Rockwell R6551 Asynchronous Communications lnterface Adapter (ACIA) provides an easily implemented, program controlled interface between 8-bit microprocessor-based systems and serial com ...

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The Rockwell R6551 Asynchronous Communications lnterface Adapter (ACIA) provides an easily implemented, program controlled interface between 8-bit microprocessor-based systems and serial communication data sets and modems.

The ACIA has an internal baud rate generator. This feature elim­inates the need for multiple component support circuits, a crystal being the only other part required. The Transmitter baud rate can be selected under program contro! to be eithec 1 of 15 different rates trom 50 to 19,200 baud, or at 1'16 times an external clock rate. The Receiver baud rate may be selected under pro­gram control to be either the Transmitter rate, or at 1/16 times an extemal clock rate. The ACIA has programmable word lengths of 5, 6, 7, or 8 bits; even, odd, or no parity; 1, 11h, or 2 stop bits.

The ACIA is designed for maximum programmed control from the microprocessor (MPU), to simplify hardware implementa­tion. TIYee separate registers permit the MPU to easily select the R6551's operating modes and data checking parameters and determine operational status.

The Command Register controls parity, receiver  echo mode, transmitter interrupt contro!, the state of the RTS line, receiver interrupt contrai, and the state of the DTR line.

The Controi Register controls the number of stop bits, word length, receiver clock source, and baud rate.

The Status Register indrcates the states of the IRQ, OSA, and DCD hnes, Transmitter and Receiver Data Registers, and Overrun, Framing, and Parity Error conditions.

The Transmitter and Receiver Data Registers are used for tem­porary data storage by the ACIA Transmit and Receiver circuits.

Features

•Compatible with 8-bit microprocessors

•Full duplex operatlon with buffered receiver and transmitter

•Data set/modem contro! functions

•Internal  baud  rate  generator  with  15 programmable baud rates (50 to 19,200)

•Program-selectable internally or externally controlled rece1ver rate

•Programmable word lengths, number of stop b1ts, and parrty bit generat1on and detection

•Programmable interrupt contro!

•Program reset

•Program-selectable serial echo mode

•Two chip selects

•2 or 1 MHz operation

•5.0 Vdc :: 5% supply requirements

•28-pin plastic or ceramic  DIP

•Full TTL compatibility

•Compatible  with  A6500,   R6500/'  and  R65COO  m1cro­ processors

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DP8303N Am 7303 Am 8303 Am 8303 CHARACTERISTICS • 8-bit bidirectional data flow reduces system package count • 3-state inputs/outputs for interfacing with bus-oriented systems • PNP ...

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DP8303N Am 7303 Am 8303 Am 8303

CHARACTERISTICS

• 8-bit bidirectional data flow reduces system package count

• 3-state inputs/outputs for interfacing with bus-oriented systems

• PNP inputs reduce input loading

• Vcc  -1.1SV VoH interfaces with TTL, MOS and CMOS

• 48mA, 300pF bus drive capability

• Am73/8303  inverting transceivers

• Am73/8304B  noninverting transceivers

• Transmit/Receive  and Chip Disable simplify contrai logie

• 20-pin ceramic and molded DIP package

• Low power - 8mA per bidirectional bit

• Advanced Schottky processing

• Bus port stays in hi-impedance state during power up/down

• 100% produci assurance screeninglo MIL-STD-883 requirements

FUNCTIONAL  DESCRIPTION

The DP8303N Am73/8303 and Am73/8304B are 8-bit 3-State Schottky transceivers. They previde bidirectional drive for bus-oriented microprocessor and digitai communications systems. Straight through bidirectional transceivers are featured, with 16mA drive capability on the A ports and 48mA bus drive capability on the B ports. PNP inputs are incorporateci to reduce input loading.

One input, TransmiVReceive determines the direction of logie signals through the bidirectional transceiver. The Chip Disable input disables both A and B ports by placing them in a 3-state condition. Chip Disable is functionally the same as an active LOW chip select.

The output high voltage (VoH) is specified at Vcc -1.1SV minimum to allow interfacing with MOS, CMOS, TTL, ROM, RAM, or microprocessors.

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