The Motorola MC68020RP16E is a CPU then replaced by the MC68030 and is part of the M68000 family.

This version is ceramic and golden.

It was produced with different frequencies, from 12 MHz to 33.33 MHz.

Features of the MC68020 series:

• Object-Code Compatible with Earlier M68000 Microprocessors
• Addressing Mode Extensions for Enhanced Support of High-Level Languages
• New Bit Field Data Type Accelerates Bit-Oriented Applications—e.g., Video Graphics
• An On-Chip Instruction Cache for Faster Instruction Execution
• Coprocessor Interface to Companion 32-Bit Peripherals—the MC68881 and MC68882 Floating-Point Coprocessors and the MC68851 Paged Memory Management Unit
• Pipelined Architecture with High Degree of Internal Parallelism Allowing Multiple Instructions To Be Executed Concurrently
• High-Performance Asynchronous Bus Is Nonmultiplexed and Full 32 Bits
• Dynamic Bus Sizing Efficiently Supports 8-/16-/32-Bit Memories and Peripherals
• Full Support of Virtual Memory and Virtual Machine
• Sixteen 32-Bit General-Purpose Data and Address Registers
• Two 32-Bit Supervisor Stack Pointers and Five Special-Purpose Control Registers
• Eighteen Addressing Modes and Seven Data Types
• 4-Gbyte Direct Addressing Range for the MC68020
• 16-Mbyte Direct Addressing Range for the MC68EC020
• Selection of Processor Speeds for the MC68020: 16.67, 20, 25, and 33.33 MHz
• Selection of Processor Speeds for the MCEC68020: 16.67 and 25 MHz

Motorola MC68020RP16E is a CPU replaced by the MC68030 and is part of the M68000 family.

It was produced with different frequencies, from 12 MHz to 33.33 MHz.

Features of the MC68020 series:

• Object-Code Compatible with Earlier M68000 Microprocessors

• Addressing Mode Extensions for Enhanced Support of High-Level Languages

• New Bit Field Data Type Accelerates Bit-Oriented Applications—e.g., Video Graphics

• An On-Chip Instruction Cache for Faster Instruction Execution

• Coprocessor Interface to Companion 32-Bit Peripherals—the MC68881 and MC68882 Floating-Point Coprocessors and the MC68851 Paged Memory Management Unit

• Pipelined Architecture with High Degree of Internal Parallelism Allowing Multiple Instructions To Be Executed Concurrently

• High-Performance Asynchronous Bus Is Nonmultiplexed and Full 32 Bits

• Dynamic Bus Sizing Efficiently Supports 8-/16-/32-Bit Memories and Peripherals

• Full Support of Virtual Memory and Virtual Machine

• Sixteen 32-Bit General-Purpose Data and Address Registers

• Two 32-Bit Supervisor Stack Pointers and Five Special-Purpose Control Registers

• Eighteen Addressing Modes and Seven Data Types

• 4-Gbyte Direct Addressing Range for the MC68020

• 16-Mbyte Direct Addressing Range for the MC68EC020

• Selection of Processor Speeds for the MC68020: 16.67, 20, 25, and 33.33 MHz

• Selection of Processor Speeds for the MCEC68020: 16.67 and 25 MHz

The 68030 is a CPU that replaced the 68020 and was replaced by the 68040.

Used in the Apple McIntosh II, UNIX stations, the Atari Falcon 03 and the Amiga della Commodore mod.3000.

The MC68030 is a 32-bit microprocessor from Motorola and is part of the M68000 family that brings together a central processing core (CPU), a data cache, an instruction cache, an improved bus controller, and a memory management unit (MMU) in a single VLSI device. The processor is designed to operate at frequencies above 20 MHz.

The MC68030 is a member of devices that combines The MC68030 is implemented with 32-bit registers and data paths, 32-bit addresses, a rich instruction set, and versatile addressing modes.

The MC68030 is upward compatible with previous processors in the M68000 family and has the addition of an MMU chip, data cache, and improved bus interface. It maintains the flexible coprocessor interface introduced in the MC68020 and provides full floating-point IEEE support through this interface with the MC68881 and MC68882 floating-point coprocessor. In addition, the internal function blocks of this microprocessor are designed to operate in parallel, allowing instructions to be executed in overlap. In addition to instruction execution, the internal caches, the on-chip MMU, and the external bus controller all run in parallel.

The MC68030 fully supports the MC68020's nonmultiplexed bus structure, with 32 bit address and 32 bit data. The MC68030 bus has an advanced controller that supports both asynchronous and synchronous bus cycles and burst data transfers. It also supports the MC68020 bus dynamic sizing mechanism that automatically determines the size of the ports, device on a cycle-by-cycle basis.