MHS 80C31
Definition
The MHS 80C31 is an 8-BIT microcontroller/microprocessor in the MCS-51 family ( 8051-class core) in a ROMLESS version, meaning it has no on-chip program ROM. It is intended for embedded systems where firmware resides in external memory, while keeping on-chip the typical family functions: CPU, internal RAM, I/O ports, TIMER/COUNTER blocks, a serial interface, and the on-chip oscillator/clock circuitry.
Memory: “from 32 to 64K of RAM” (correct system-level view)
When it is said that it can include “from 32 to 64K of RAM”, in practice this refers to the addressable external RAM (external data space) that the designer can size according to the board:
Configurations with smaller external RAM (for example 32 KB) for compact applications.
Configurations with external RAM up to 64K when larger buffers, tables, or data areas are required.
In parallel, the chip also includes a small internal RAM (typically 128 BYTE) useful for the stack and low-latency “hot” variables.
I/O lines: 32 parallel lines
The 32 I/O lines correspond to 4 ports of 8 bits each. These ports can be used:
As general-purpose digital I/O (sensor inputs, outputs to LEDs/relays via drivers, etc.).
As multiplexed lines for an external bus (especially Port 0/Port 2 in classic 8051 configurations with external memory).
Timers/counters: three 16-bit counters/timers
The profile you provided includes three 16-BIT TIMER/COUNTER blocks, used for:
System time-base and periodic ticks.
Event counting (pulses on dedicated pins).
Timing for protocols and control sequences.
Technical note: in some “classic 8051” implementations there are two timers; in more advanced variants (often within extended 80C31/80C32-type families) a third timer block exists. In this report I preserved the profile you requested (three timers).
Serial port: multiprocessor, I/O expansion, full-duplex UART
The integrated serial port is typically a full-duplex UART, usable in three practical ways:
Multiprocessor communications: a mode with address recognition/filtering, useful on shared multi-drop serial buses (multiple nodes).
I/O expansion: connection to shift registers, serial expanders, or subsystems that reduce parallel wiring.
Full-duplex UART: bidirectional communications with peripherals, diagnostics, service console, or industrial interfaces (via external transceivers).
On-chip oscillator and clock
The device integrates the oscillator and clock circuitry:
This integration simplifies the board and makes execution timing, as well as peripheral timing (timers/serial), more predictable.
Sketch of the most important connections
┌──────────────────────────────┐
│ EPROM / FLASH │
│ (external program) │
└──────────────┬───────────────┘
│ code bus (addr/data + control)
▼
┌──────────────────┐
│ MHS 80C31 │
│ ROMLESS 8-BIT MCU│
│ internal RAM │
│ 32 I/O │
│ 3× 16-BIT TIMERS │
│ full-duplex UART │
│ on-chip OSC/CLK │
└───────┬──────────┘
│
├────────► Parallel I/O → sensors / drivers / latches / LEDs
│
├────────► UART → multiprocessor / expansion / debug
│
└────────► (opt.) external RAM → 32K…64K (data space)
Table 1 – Identification data and specifications (English)
| Characteristic | Typical value |
|---|
| Device | MHS 80C31 |
| Class | 8-BIT MICROCONTROLLER / MICROPROCESSOR ( MCS-51 family, 8051-class core) |
| On-chip program ROM | Not present ( ROMLESS device) |
| Addressable external RAM | Typically 32K…64K (design-dependent) |
| Parallel I/O | 32 lines (4 × 8-bit ports) |
| Timers/counters | 3 × 16-BIT TIMER/COUNTER |
| Serial | UART port: multiprocessor / I/O expansion / full duplex |
| Clock | On-chip oscillator and clock circuitry |
Table 2 – Operational and design aspects (English)
| Aspect | Practical meaning |
|---|
| Firmware in external memory | Easy update (swap/reprogram memory) and larger programs |
| Scalable external RAM | From compact systems (32K) to richer systems (64K) without changing architecture |
| 32 I/O lines | Direct interfacing to external logic; can be used as a multiplexed external bus |
| 3 × 16-bit timers | Time-base, event counting, and timing without dedicated external logic |
| Multiprocessor UART | Shared serial bus with multiple nodes, cleaner addressing and traffic handling |
| On-chip OSC/CLK | Reduced BOM and more controlled timing for serial and timers |
MHS P-80C31 
