SGS Z84000BB1

The Z84000 is a CPU in the Z80 series produced by Zilog and SGS. In the stated context, it runs at 6 MHZ and is remembered as one of the most widespread CPUs in both personal computers and industrial electronics, thanks to an architecture that is straightforward to integrate, a broad instruction set, and high functional density for systems built around external memory and I/O.

Practically, it is an 8-bit CPU with “extended” internal resources (registers and addressing capabilities) that allow relatively complex firmware while keeping the hardware platform linear (RAM/ROM + bus peripherals).

Programming features: registers and internal R/W memory

The CPU provides 208 bits of read/write memory accessible to the programmer. In addition, it includes a register file typical of the series:

• An accumulator and six 8-bit registers, pairable as three 16-bit registers.

• A 16-bit stack pointer and a 16-bit program counter.

• Two 16-bit index registers, useful for indexed addressing and efficient handling of data structures and buffers.

Practically, this model makes routines on arrays, stack usage, and interrupt contexts easier, reducing repeated RAM accesses for “hot” variables.

Address bus and memory space: 16-bit, 64 KB directly addressable

The core exposes a 16-bit address bus, therefore it can directly access 64 KB of address space. In a typical system this means:

• Up to 64 KB of program memory (ROM/EPROM/FLASH).

• Up to 64 KB of data memory (RAM), depending on the system map.

• Space that can also be dedicated to I/O through decoding and mapping (platform-dependent).

The practical result is that the board architecture revolves around the memory map and address-decoding logic, which determine how ROM, RAM, and peripherals share the address space.

Instruction set: root instructions and prefix-extended instructions

The CPU provides 252 root instructions and uses 4 reserved bytes as prefixes to extend the set, reaching 308 additional instructions.

In practical terms:

• The “base” instructions cover the main flow (loads, branches, arithmetic/logic).

• Prefixed instructions extend capabilities (richer addressing, more specialized operations) at the cost of some cycles and more complex encoding.

Core design: synchronous, no internal tri-states, reusable in ASIC/FPGA

The core is described as microcode-free, developed for reuse in ASIC and FPGA implementations. It is also strictly synchronous, with no internal tri-states and a synchronous reset.

Practical implications:

• Better timing predictability and easier integration in modern digital logic flows.

• Fewer ambiguities associated with internal tri-state buses, simplifying verification and timing closure in hardware implementations.

Main functional units

Control unit
Includes an 8-bit instruction decoder for instruction decoding and internal control-signal generation.

Arithmetic-logic unit
Supports:

• 8-bit arithmetic and logical operations.

• 16-bit arithmetic operations.

• Boolean (bit-level) manipulations.

Register file unit
Includes:

• A duplicate set of general-purpose registers and flag registers (useful for fast context switches and interrupt handling).

• Two 16-bit index registers.

Interrupt controller
Handles:

• Three modes of maskable interrupts.

• A non-maskable interrupt (NMI).

External memory and I/O interface

The external interface supports addressing up to:

• 64 KB of program memory.

• 64 KB of data memory.

• 64 KB of input/output devices.

An on-core dynamic memory refresh counter is also present, useful in systems that use DRAM and require periodic refresh coordinated by the processor.

Sketch of the most important connections

                 16-bit address bus + 8-bit data bus + control
        ┌──────────────────────────────────────────────────────────┐
        │              system logic / address decoding              │
        │  ROM/EPROM, RAM, I/O, interrupts, optional DRAM refresh   │
        └───────────────────────────────┬──────────────────────────┘
                                        │
                                        ▼
                           ┌─────────────────────────────┐
                           │           Z84000             │
                           │     Z80-series CPU @ 6 MHZ    │
                           │  16-bit SP/PC, 16-bit indexes │
                           │  interrupts + refresh counter │
                           └─────────────┬───────────────┘
                                         │
                                         ├────────► program memory (up to 64 KB)
                                         ├────────► data memory (up to 64 KB)
                                         └────────► I/O (up to 64 KB, platform mapping dependent)

Table 1 – Identification data and specifications

Table 2 – Operational and design considerations