Intel D8085AH ceramic version

The 8085 is an 8-bit microprocessor designed by Intel and introduced in the second half of the 1970s as a more “integrated” evolution of the 8080. It is software-compatible with the 8080 at the instruction-set level, but it simplifies system integration thanks to key features: a single +5 V supply, an on-chip clock generator, and built-in interfaces (a richer interrupt system and a simple 1-bit serial interface).

In practice, it is a CPU intended for systems with external RAM/ROM and I/O, on a parallel bus, typical of industrial controllers, instrumentation, and educational/hobby designs.

Bus and addressing: 8-bit data, 16-bit addresses (64 KB)

The 8085 uses:

• 8-bit data bus.

• 16-bit address bus, therefore up to 64 KB address space.

• AD0–AD7 multiplexed lines (low address + data): during the first phase of the bus cycle they carry the low address, then they become the data bus.

• Dedicated A8–A15 lines for the high address.

• ALE (address latch enable) to “capture” the low address into an external latch and keep it stable during the data transfer.

Practical consequence: an external latch such as 74LS373/8282 (or equivalent) is almost always used to separate A0–A7 from the data bus.

Power and clock: why the 8085 was easier to integrate

Compared to the 8080 (which required multiple supply voltages), the 8085 operates from a single +5 V supply, reducing regulators and board complexity.

It also integrates a clock generator: with an external crystal or an RC/LC network, the internal clock can be derived without a separate clock generator as in classic 8080 systems. Typical frequencies depend on the speed grade and are on the order of 3–6 MHZ.

Registers and programming model: minimal but effective

The logical model includes:

• Accumulator A and the flag register.

• General registers B, C, D, E, H, L (also usable as pairs BC, DE, HL).

• 16-bit PC (program counter) and 16-bit SP (stack pointer).

Practically, the register-pair organization makes pointers and address-oriented operations convenient while remaining in an 8-bit paradigm.

Interrupts and 1-bit serial: event control and simple links

The 8085 adds a more articulated interrupt system, with:

• TRAP (non-maskable, highest priority).

• RST 7.5, RST 6.5, RST 5.5 (maskable and vectored).

• INTR (generic interrupt request, with external acknowledge).

It also includes a minimal 1-bit serial interface:

• SID (serial input data).

• SOD (serial output data).

In practice, SID/SOD are useful for slow signals, simple diagnostics, synchronization, or bit-banged links, without replacing a full UART.

Sketch of the most important connections

                 A8..A15 (high address) + AD7..AD0 (low addr / data)
        ┌──────────────────────────────────────────────────────────┐
        │                         8085                              │
        │  A8..A15 ────────────────────────────────► address bus     │
        │  AD0..AD7 ───────┬───────────────► data bus (D0..D7)       │
        │                  │                                          │
        │  ALE ───────────►│ latch enable                             │
        │                  ▼                                          │
        │             ┌───────────┐                                   │
        │             │  LATCH    │  (e.g., 74LS373/8282)              │
        │             └───────────┘                                   │
        │                  │                                          │
        │                  └──────────────► A0..A7 (low address)       │
        │                                                          │
        │  RD/WR, IO/M ─────────────────► memory/I-O cycle controls   │
        │  TRAP, RST7.5/6.5/5.5, INTR ──► interrupts                  │
        │  SID/SOD ─────────────────────► 1-bit serial                │
        └──────────────────────────────────────────────────────────┘
                         │
                         ├────────► ROM (firmware)
                         ├────────► RAM (data/stack)
                         └────────► I/O (memory-mapped or I/O-mapped)

Table 1 – Identification data and specifications

Table 2 – Operational and design considerations