A DUART (dual asynchronous receiver/transmitter) is an IC that integrates two independent UART channels, each full-duplex, to handle asynchronous serial communications (typical RS-232/TTL style) with lower host CPU overhead than discrete solutions. A DUART combines two programmable serial channels with internal clocking (oscillator + clock selection), a baud rate generator, a programmable counter/timer, interrupt logic, and auxiliary I/O ports.
What it provides beyond a single UART
This device targets systems that need two serial lines with robust control and flexibility:
Two independent channels (A and B), each with programmable framing (data bits, parity, stop bits) and independently selectable Tx/Rx speeds.
Receiver buffering: the receiver is quadruple-buffered, reducing overrun risk and lowering interrupt/poll overhead.
Speed selection: baud rate selection from a built-in set (up to 115.2 kbaud in the family specification) and/or clocks derived from the counter/timer or external inputs.
Programmable 16-bit counter/timer: used as a time base, for non-standard baud generation, or for square-wave/timed outputs depending on configuration.
Auxiliary ports: typically a multi-purpose input port (e.g., 7-bit) and a multi-purpose output port (e.g., 8-bit) usable as GPIO or mapped to internal functions (interrupt output, handshake, clock, status).
Flow control: capability to inhibit a remote transmitter when the local receive buffering is full (commonly via RTS/CTS-style mechanisms or equivalent programmable functions).
Programming model (registers and driver flow)
Programming follows a per-channel register set:
Mode registers (e.g., MR1/MR2): define frame format (5–8 bits, parity, stop bits, special modes).
Clock select (CSR): selects the clock/baud source for Tx and Rx.
Command register (CR): enables/disables Tx/Rx, clears errors, controls break and operational functions.
Status register (SR): indicates Tx ready/Rx ready, line errors (parity, framing, overrun), and buffer conditions.
THR/RHR: transmit holding and receive holding registers used to write outgoing bytes and read incoming bytes.
A typical driver configures channel A and B, sets baud and framing, enables receive interrupts, then services I/O via interrupts (or polling) by reading RHR when RxRDY is asserted and writing THR when TxRDY is asserted.
Clocking, baud, and the counter/timer
This DUART class can operate from a crystal or external clock, using an internal baud rate generator and a programmable counter/timer to produce standard or custom rates. Separate clock selection per channel supports “dual-speed” use cases where channels (or Tx/Rx) run at different speeds.
Sketch of the most important connections (typical topology)
┌───────────────────────────┐
│ CPU / MCU │
│ D[7..0] A[ ] /RD /WR │
│ /CS /IRQ (I/O bus) │
└──────────────┬────────────┘
│
▼
┌──────────────────┐
│ DUART SCN2681 │
│ Ch.A: RxA/TxA │───►/◄── Line driver (TTL↔RS-232) ─► serial A
│ Ch.B: RxB/TxB │───►/◄── Line driver (TTL↔RS-232) ─► serial B
│ Baud gen + C/T │
│ IP[ ] / OP[ ] │───► GPIO / handshake / status
└───────┬──────────┘
│
Xtal/clk in
