An FFT address sequencer is a dedicated hardware generator that outputs the full, cycle-accurate sequence of data (RAM) addresses and coefficient (ROM) addresses required to execute the repetitive FFT butterfly operations. Instead of spending controller bandwidth (or microcode ROM space) on index arithmetic, stride patterns, and bit-reversal, the sequencer emits the correct address stream once you select the FFT type and transform length.

What it does in a real system

• Produces a time-ordered address stream for reading the two butterfly inputs and writing back the results, aligned to the system clock.

• Generates (or synchronizes) coefficient addresses so twiddle factors are fetched exactly when the datapath needs them.

• Supports multiple FFT variants by hardware mode selection: DIT/DIF, radix-2/radix-4, in-place / non-in-place, and bit-reverse handling (pre-scrambled vs not).

Why this matters (architecture perspective)

Classic microcoded FFT engines often had plenty of arithmetic throughput but were bottlenecked by address generation: butterfly scheduling forces structured but non-trivial permutations, especially with bit-reversal and ping-pong buffering. A part like Am29540 reduces control complexity: the controller sets the transform characteristics and then drives a small instruction/clock interface while the chip handles address sequencing end-to-end.

Identification data and key specifications (table)

Key control and I/O concepts (how you “drive” it)

• Mode selection inputs: controls for RADIX 4/2, DIT/DIF, and a selection for sequences compatible with pre-bit-reversed (“pre-scrambled”) data (noted as PSD in AMD material).

• Transform length inputs (TL3–TL0): a small field that encodes the transform length; the length is captured at the start of the FFT run.

• Butterfly counter instructions: the internal butterfly counter advances on the rising edge and responds to four functional commands: COUNT, RESET, RESET/LOAD, HOLD.

• Bidirectional 3-state address port + offset load: during RESET/LOAD, an address offset can be loaded through the address port; the offset is effectively OR-combined into the unused high-order address bits for the selected length.

• Status outputs:

  • EVEN/ODD: supports read/write bank alternation in non-in-place architectures; in RVI sequences it maps to KNZ/KZ behavior.

  • IT COMP: marks the end of an iteration (“bottom of a column” of butterflies), useful for block-floating scaling.

  • FFT COMP: marks the last butterfly of the transform.

Sketch of the most important connections

                      ┌──────────────────────────────┐
                      │     Controller / microcode    │
                      │   (or external FSM/PLA)       │
                      └──────────────┬───────────────┘
                                     │
            FFT mode + length        │   step / init control
 RADIX4/2, DIT/DIF, PSD, TL[3:0]     │   COUNT / RESET / LOAD / HOLD
                                     ▼
                         ┌─────────────────────────┐
                         │  FFT address sequencer  │
                         │       (Am29540)         │
                         │                         │
                         │  ADDRESS[ ] ────────────┼──► RAM address (data)
                         │                         │
                         │  (coeff addr) ──────────┼──► ROM / sin-cos / twiddle
                         │                         │
                         │  EVEN/ODD ──────────────┼──► bank select / R-W swap
                         │  IT COMP  ──────────────┼──► iteration boundary
                         │  FFT COMP ──────────────┼──► end of transform
                         └──────────────┬──────────┘
                                        │
                                        ▼
                           ┌────────────────────────┐
                           │ Butterfly datapath      │
                           │ (complex add/mul/MAC)   │
                           └────────────────────────┘

Addressing choices and architecture mapping (table)