CMOS STATIC RAM (SRAM)

Definition

CMOS STATIC RAM (SRAM) is a VOLATILE random-access memory that retains data as long as power is applied, without requiring periodic refresh. “STATIC” means each bit remains stable thanks to an internal bistable cell (latch), while “CMOS” refers to the fabrication technology which, compared to older implementations, enables lower power consumption (especially in standby) and good speed/efficiency for many embedded and caching applications.

Unlike DRAM, SRAM does not require refresh cycles and offers very low latency; in exchange, for the same capacity it uses more silicon area and costs more.

Operating principle (memory cell)

The classic SRAM cell is a 6T (six-transistor) cell:

• Two cross-coupled inverters form a latch that stores the logic state (0/1).

• Two access transistors connect the cell to the bitlines during read/write, controlled by the wordline (row select).

With power present, the latch maintains its state without periodic operations. If power is removed, contents are lost (volatile memory).

Main operating characteristics

• No refresh: simplifies the controller and reduces timing jitter.

• Fast access: access times typically lower than DRAM and often deterministic (especially for asynchronous SRAM).

• Low standby power: CMOS technology enables low data-retention currents, useful for battery-powered devices or deep sleep modes.

• Simple interface: many SRAM devices are asynchronous, using direct control signals (CE/OE/WE) with no clock.

• Cost/area: the 6T cell is “large” compared to DRAM (1T+capacitor), so density is lower and cost per bit is higher.

Common types of CMOS SRAM

• Asynchronous SRAM: simple interface, no clock, widely used as external memory for CPU/MCU, buffers, and linear video memory.

• Synchronous SRAM: uses CLK and internal pipelining (e.g., SYNC SRAM, PIPELINED SRAM) for high throughput, typical in higher-performance systems.

• Low-power / battery-backup SRAM: optimized for very low standby currents and often designed for data retention with a backup battery (via an external supply switchover circuit).

Interface and typical signals (asynchronous SRAM)

An asynchronous CMOS SRAM commonly presents:

• Address bus A[ ]: selects the location.

• Data bus D[ ]: bidirectional.

• CE (/CE or /CS): chip enable (enables the device).

• OE (/OE): output enable (enables the output during read).

• WE (/WE): write enable (enables write).

• Optional /UB /LB (byte enables) on 16-bit parts to select upper/lower byte.

Read and write operations occur based on control-signal combinations and minimum timing requirements (setup/hold, pulse width, access time).

Typical timing parameters (what they really mean)

• tAA (address access time): time from valid address to valid data at the output.

• tCE (chip enable access time): time from CE asserted to valid data.

• tOE (output enable access time): time from OE asserted to valid data.

• tWC (write cycle time): minimum write-cycle duration.

• tWP (write pulse width): minimum WE pulse width.

• tDH/tDS (data hold/setup): data hold and setup requirements relative to WE/CE.

In practice: to guarantee correctness, the host must keep address and data stable for the specified timing windows.

Typical applications

• Cache and low-latency working memory (when not integrated on-chip).

• Buffers for communications (packets, logical FIFOs, ring buffers).

• Video memory/line buffers in simple systems or retrocomputing.

• Tables and deterministic lookup (DSP, industrial control).

• Temporary storage in real-time systems where predictability matters more than density.

Advantages and limits (technical summary)

Advantages:

• Low latency, deterministic behavior.

• No refresh, simple controller.

• Good standby energy efficiency (CMOS).

Limits:

• Worse density and higher cost per bit than DRAM.

• Volatile: loses data without power (unless backup solutions are used).

• Capacities are typically smaller than DRAM at comparable cost.

Sketch of the most important connections (asynchronous SRAM)

                 ┌──────────────────────────────┐
                 │            CPU / MCU          │
                 │ A[ ]  D[ ]  /RD  /WR          │
                 │ (address decode /CS logic)    │
                 └──────────────┬───────────────┘
                                │  A[ ] + D[ ] + controls
                                ▼
                       ┌──────────────────┐
                       │  CMOS STATIC RAM │
                       │     (SRAM)       │
                       │ A[ ]  D[ ]       │
                       │ /CE  /OE  /WE    │
                       │ (opt. /UB /LB)   │
                       └──────────────────┘

Table 1 – Identification data and specifications

Table 2 – Main signals and timing