Zilog Z8410APS: Z80 DMA 

Definition

The Zilog Z8410APS  is a direct memory access controller for Z80-based systems that moves data blocks without involving the CPU for every byte. The idea is straightforward: the CPU configures the DMA (source, destination, length, and mode), then the DMA temporarily takes control of the bus and transfers data between memory ↔ memory, I/O ↔ memory, or I/O ↔ I/O (depending on configuration and system glue logic), dramatically reducing overhead and jitter compared to polling or software copy loops.

What it adds compared to a CPU copy loop

• Frees CPU cycles: the CPU does not execute repetitive IN/OUT/LD instructions for each byte.

• Deterministic transfers: for many workloads, DMA provides more regular and predictable throughput.

• Bus management: the DMA synchronizes with slower peripherals through READY/WAIT signals and can operate in modes that minimize impact on the rest of the system.

• End-of-block notification: at the end of a transfer it can signal an event (interrupt or flag), useful for block-oriented drivers.

Functional architecture (how to think about the chip)

A practical model is a “data-move engine” with:

• A byte counter defining the block size.

• A source pointer and a destination pointer (address counters) that auto-increment/decrement according to mode.

• A bus arbitration unit that requests the bus, waits for a safe window, and then performs read/write cycles.

• Handshake logic to synchronize with peripherals (ready, wait, request/ack when implemented on the board).

• Interrupt and daisy-chain logic in the Zilog Z80 style for clean integration with other Z80 peripherals.

Important note: the Z80 DMA is typically a single-channel controller (one DMA stream at a time). If multiple channels are needed, historically designers used multiple chips or external multiplexing/arbiter logic.

Typical operating modes

In real Z80 systems, the Z8410 is most often used in these modes:

• Burst mode: the DMA “holds” the bus and transfers the block (or a large portion) as fast as possible. Maximum throughput, but the CPU is stalled longer.

• Cycle stealing (interleaving): the DMA steals single cycles (or small groups) between CPU cycles. Lower impact on responsiveness, with slightly reduced throughput.

• Handshake-driven transfers: when a peripheral cannot accept data at full speed, synchronization signals (ready/wait/req-ack depending on board design) ensure the DMA does not outrun the device.

• Auto-initialize / restart: in some configurations an automatic reload of parameters can be arranged (useful for repetitive streams or circular buffers, if supported by the chosen control scheme).

Typical use cases in Z80 systems

• Fast block loading into RAM (e.g., from a parallel peripheral or an external FIFO).

• Display updates: copying frame buffers or regions of video memory (when the architecture allows it).

• High-rate I/O: data acquisition from parallel ADCs, instruments, or custom interfaces with handshake.

• Block movement for protocols: handling frames or packets on relatively “dumb” interfaces, leaving the CPU only headers and control flow.

Interface to the Z80 CPU (bus and main signals)

From the hardware point of view, the Z80 DMA connects to the bus using standard Z80 signals:

• D[7..0]: data bus for programming and for some I/O transfer cycles.

• /IORQ, /RD, /WR: I/O cycles to access control registers (and for DMA operations involving I/O peripherals).

• /MREQ (in many systems): used during transfers to/from memory.

• /BUSREQ /BUSACK: bus request and bus grant (fundamental: this is how the DMA “inserts itself” without conflicts).

• /INT, IEI/IEO: interrupt and daisy-chain lines like other Zilog peripherals.

• /RESET, CLK: reset and system clock.

Sketch of the most important connections

                 ┌───────────────────────────┐
                 │            Z80 CPU         │
                 │ D[7..0]  /IORQ /RD /WR     │
                 │ /MREQ  /BUSREQ /BUSACK     │
                 │ /INT   IEI/IEO  CLK RESET  │
                 └──────────────┬────────────┘
                                │ system bus
                                ▼
                       ┌──────────────────┐
                       │     Z80 DMA      │  (Z8410)
                       │  src/dst addr    │
                       │  byte counter    │
                       │  bus arbiter     │
                       │  handshake/IRQ   │
                       └───┬───────────┬──┘
                           │           │
                 memory cycles          │ I/O cycles + handshake
                           ▼           ▼
                 ┌────────────────┐   ┌─────────────────────┐
                 │ RAM / ROM      │   │ I/O peripheral       │
                 │ (source/dest)  │   │ (UART, PIO, FIFO,    │
                 └────────────────┘   │  ADC, interface…)    │
                                      └─────────────────────┘

Programming (driver view)

At the driver level, the conceptual steps are always the same:

1. Define the direction (mem→mem, I/O→mem, mem→I/O, etc.).

2. Set source address and destination address (and whether to increment/decrement).

3. Load the byte count for the block.

4. If needed, configure handshake/wait and select the mode (burst or cycle stealing).

5. Enable an optional end-of-block interrupt.

6. Start the transfer and let the DMA complete, checking status or receiving an IRQ.

Table 1 – Operational characteristics 

Table 2 – Signals and integration