The Philips Semiconductors SCN2681 Dual Universal Asynchronous Receiver/Transmitter (DUART) is a single-chip MOS-LSI communications device that provides two independent full-duplex asynchronous receiver/transmitter channels in a single package.  It interfaces directly with microprocessors  and may be used in a polled or interrupt driven system.
The operating mode and data format of each channel can be programmed independently.  Additionally, each receiver and transmitter can select its operating speed as one of eighteen fixed baud rates, a 16X clock derived from a programmable counter/timer, or an external 1X or 16X clock.  The baud rate generator and counter/timer can operate directly from a crystal or from external clock inputs.  The ability to independently program the operating speed of the receiver and transmitter make the DUART particularly attractive for dual-speed channel applications such as clustered terminal systems.
Each receiver is quadruply buffered to minimize the potential of receiver over-run or to reduce interrupt overhead in interrupt driven systems.  In addition, a flow control capability is provided to disable a remote DUART transmitter when the buffer of the receiving device is full.
Also provided on the SCN2681 are a multipurpose 7-bit input port and a multipurpose 8-bit output port. These can be used as general purpose I/O ports or can be assigned specific functions (such as clock inputs or status/interrupt outputs) under program control.
The SCN2681 is available in three package versions: 40-pin and 28–pin, both 0.6” wide DIPs; a compact 24-pin 0.4” wide DIP; and a 44-pin PLCC.

FEATURES

• Dual full-duplex asynchronous receiver/transmitter

• Quadruple buffered receiver data registers

• Programmable data format – 5 to 8 data bits plus parity – Odd, even, no parity or force parity – 1, 1.5 or 2 stop bits programmable in 1/16-bit increments

• Programmable baud rate for each receiver and transmitter selectable from: – 22 fixed rates: 50 to 115.2k baud

• 16-bit programmable Counter/Timer – Non-standard rates to 115.2Kb – One user-defined rate derived from programmable timer/counter – External 1X or 16X clock

• Parity, framing, and overrun error detection • False start bit detection • Line break detection and generation • Programmable channel mode – Normal (full-duplex) – Automatic echo – Local  loopback – Remote loopback • Multi-function programmable 16-bit counter/timer

• Multi-function 7-bit input port – Can  serve as clock or control inputs – Change of state detection on four inputs – 100kΩ typical pull-up resistor

• Multi-function 8-bit output port – Individual bit set/reset capability – Outputs can be programmed to be status/interrupt signals

• Versatile interrupt system – Single interrupt output with eight maskable interrupting conditions – Output port can be configured to provide a total of up to six separate wire-ORable interrupt outputs

• Maximum data transfer: 1X – 1MB/sec, 16X – 125kB/sec

• Automatic wake-up mode for multidrop applications • Start-end break interrupt/status

• Detects break which originates in the middle of  a character • On-chip crystal oscillator

• Single +5V power supply

• Commercial and industrial temperature ranges available

• DIP and PLCC packages

• Eight general-purpose floating-point data registers, each supporting a full 80-bit extended precision real data format
• A 67-bit arithmetic unit to allow very fast calculations, with intermediate precision greater than the extended-precision format.
• A 67-bit barrel shifter for high speed shifting operations
• Special purpose hardware for high speed conversion of binary real memory operations and from the internal extended format
• Reduced coprocessor interface overhead to increase throughput
• 46 instructions, including 35 arithmetic operations
• Full conformance to IEE 754 standard, including a full set of trigonometric and transcenental functions
• Seven data types: bytes, words and long-words integers; single, double, extended-precision real numbers and packed binary-coded decimal (BCD) string real numbers
• 22 constants available in the on-chip ROM including π, e, and powers of 10
• Virtual memory / machine operations
• Efficient mechanism for procedure calls, context switches and interrupt handling
• Concurrent instruction execution with the main processor
• Concurrent instruction execution of multiple floaying-point instructions
• Use with any host processor on an 8, 16 or 32 bit data bus

The Motorola MC68020RP16E is a CPU then replaced by the MC68030 and is part of the M68000 family.

This version is ceramic and golden.

It was produced with different frequencies, from 12 MHz to 33.33 MHz.

Features of the MC68020 series:

• Object-Code Compatible with Earlier M68000 Microprocessors
• Addressing Mode Extensions for Enhanced Support of High-Level Languages
• New Bit Field Data Type Accelerates Bit-Oriented Applications—e.g., Video Graphics
• An On-Chip Instruction Cache for Faster Instruction Execution
• Coprocessor Interface to Companion 32-Bit Peripherals—the MC68881 and MC68882 Floating-Point Coprocessors and the MC68851 Paged Memory Management Unit
• Pipelined Architecture with High Degree of Internal Parallelism Allowing Multiple Instructions To Be Executed Concurrently
• High-Performance Asynchronous Bus Is Nonmultiplexed and Full 32 Bits
• Dynamic Bus Sizing Efficiently Supports 8-/16-/32-Bit Memories and Peripherals
• Full Support of Virtual Memory and Virtual Machine
• Sixteen 32-Bit General-Purpose Data and Address Registers
• Two 32-Bit Supervisor Stack Pointers and Five Special-Purpose Control Registers
• Eighteen Addressing Modes and Seven Data Types
• 4-Gbyte Direct Addressing Range for the MC68020
• 16-Mbyte Direct Addressing Range for the MC68EC020
• Selection of Processor Speeds for the MC68020: 16.67, 20, 25, and 33.33 MHz
• Selection of Processor Speeds for the MCEC68020: 16.67 and 25 MHz

Motorola MC68020RP16E is a CPU replaced by the MC68030 and is part of the M68000 family.

It was produced with different frequencies, from 12 MHz to 33.33 MHz.

Features of the MC68020 series:

• Object-Code Compatible with Earlier M68000 Microprocessors

• Addressing Mode Extensions for Enhanced Support of High-Level Languages

• New Bit Field Data Type Accelerates Bit-Oriented Applications—e.g., Video Graphics

• An On-Chip Instruction Cache for Faster Instruction Execution

• Coprocessor Interface to Companion 32-Bit Peripherals—the MC68881 and MC68882 Floating-Point Coprocessors and the MC68851 Paged Memory Management Unit

• Pipelined Architecture with High Degree of Internal Parallelism Allowing Multiple Instructions To Be Executed Concurrently

• High-Performance Asynchronous Bus Is Nonmultiplexed and Full 32 Bits

• Dynamic Bus Sizing Efficiently Supports 8-/16-/32-Bit Memories and Peripherals

• Full Support of Virtual Memory and Virtual Machine

• Sixteen 32-Bit General-Purpose Data and Address Registers

• Two 32-Bit Supervisor Stack Pointers and Five Special-Purpose Control Registers

• Eighteen Addressing Modes and Seven Data Types

• 4-Gbyte Direct Addressing Range for the MC68020

• 16-Mbyte Direct Addressing Range for the MC68EC020

• Selection of Processor Speeds for the MC68020: 16.67, 20, 25, and 33.33 MHz

• Selection of Processor Speeds for the MCEC68020: 16.67 and 25 MHz

The 68030 is a CPU that replaced the 68020 and was replaced by the 68040.

Used in the Apple McIntosh II, UNIX stations, the Atari Falcon 03 and the Amiga della Commodore mod.3000.

The MC68030 is a 32-bit microprocessor from Motorola and is part of the M68000 family that brings together a central processing core (CPU), a data cache, an instruction cache, an improved bus controller, and a memory management unit (MMU) in a single VLSI device. The processor is designed to operate at frequencies above 20 MHz.

The MC68030 is a member of devices that combines The MC68030 is implemented with 32-bit registers and data paths, 32-bit addresses, a rich instruction set, and versatile addressing modes.

The MC68030 is upward compatible with previous processors in the M68000 family and has the addition of an MMU chip, data cache, and improved bus interface. It maintains the flexible coprocessor interface introduced in the MC68020 and provides full floating-point IEEE support through this interface with the MC68881 and MC68882 floating-point coprocessor. In addition, the internal function blocks of this microprocessor are designed to operate in parallel, allowing instructions to be executed in overlap. In addition to instruction execution, the internal caches, the on-chip MMU, and the external bus controller all run in parallel.

The MC68030 fully supports the MC68020's nonmultiplexed bus structure, with 32 bit address and 32 bit data. The MC68030 bus has an advanced controller that supports both asynchronous and synchronous bus cycles and burst data transfers. It also supports the MC68020 bus dynamic sizing mechanism that automatically determines the size of the ports, device on a cycle-by-cycle basis.